Abstract-Design of switching-mode CMOS frequency multipliers in sub-Terahertz regime

Jung-Dong Park¹⁾

1) Graduate of School of Engineering, University of California

https://www.jstage.jst.go.jp/article/elex/11/18/11_11.20140806/_article
Switching mode CMOS frequency multipliers are studied in sub-Terahertz regime. Analysis on the multiplier architectures and optimal gate bias at CMOS switch are investigated to maximize output power at designated harmonics. Utilizing a differential pair, a 195 GHz tripler having a hair-pin filter is designed to maximize 3^rd harmonics with −14.8 dB of conversion gain (CG) from P_in = +13 dBm of the balanced input, while the 260 GHz quadrupler utilizes quadruple-push pairs which achieves CG = −16 dB from two +13 dBm of the balanced I/Q driving signals in a 65 nm digital CMOS process.

Abstract-Design of Switching-Mode CMOS Frequency Multipliers in Sub-Terahertz Regime

Jung-Dong Park¹⁾

1) Graduate of School of Engineering, University of California

 [Advance Publication] Released September 03, 2014

https://www.jstage.jst.go.jp/article/elex/advpub/0/advpub_11.20140806/_article

Switching mode CMOS frequency multipliers are studied in sub-Terahertz regime. Analysis on the multiplier architectures and optimal gate bias at CMOS switch are investigated to maximize output power at designated harmonics. Utilizing a differential pair, a 195GHz tripler having a hair-pin filter is designed to maximize 3^rd harmonics with -14.8dB of conversion gain (CG) from P_in=+13dBm of the balanced input, while the 260GHz quadrupler utilizes quadruple-push pairs which achieves CG=-16dB from two +13dBm of the balanced I/Q driving signals in a 65nm digital CMOS process.

Abstract-Fully Integrated Silicon Terahertz Transceivers for Sensing and Communication Applications

Jung-Dong Park

http://www.eecs.berkeley.edu/Pubs/TechRpts/2013/EECS-2013-36.html

With advancement of the silicon device, we have witnessed revolutionary achievements in RF and millimeter-wave integrated circuit (IC) technology during last decade. Reflecting the impact of the RFICs in its compactness, low-cost, and mass production, the Terahertz Silicon Integrated Circuit (THz-IC) will open a new era in imaging, sensing, spectroscopy, and ultrafast wireless communication. This thesis mainly explores two fully integrated terahertz transceivers for sensing and communication applications in well matured 0.13 µm BiCMOS and 65 nm digital CMOS technology. Since antenna size shrinks quadratically as radiation frequency increases for a given gain, on-chip antennas have great potential in terahertz range by eliminating packaging issues for cost-effective, compact terahertz transceivers. To achieve high radiation efficiency, we investigate the loss mechanisms of several on-chip antennas implemented in conventional (Bi) CMOS technologies. By introducing a compact N-push clamping harmonic generator utilizing the transformer-coupled push-push structure with Coplanar Stripline (CPS), the fundamental signal filtering is effectively achieved by highly rejecting the common-mode input. The designed N-push harmonic generator with proposed architecture is robust to the phase mismatch in driving signals. A 0.38 THz Frequency Modulated Continuous Wave (FMCW) radar transceiver is presented with the ranging and detection of a target in 10 cm. A 0.26 THz fully integrated CMOS transceiver is demonstrated for wireless chip to chip communication. The non-coherent On-Off Keying (OOK) transceiver with dual antenna chains is implemented to overcome the limited device performance in 65 nm CMOS which achieves +5 dBm of the Equivalent Isotropically Radiated Power (EIRP).

Advisor: Ali Niknejad