Abstract-Design of switching-mode CMOS frequency multipliers in sub-Terahertz regime

Jung-Dong Park¹⁾

1) Graduate of School of Engineering, University of California

https://www.jstage.jst.go.jp/article/elex/11/18/11_11.20140806/_article
Switching mode CMOS frequency multipliers are studied in sub-Terahertz regime. Analysis on the multiplier architectures and optimal gate bias at CMOS switch are investigated to maximize output power at designated harmonics. Utilizing a differential pair, a 195 GHz tripler having a hair-pin filter is designed to maximize 3^rd harmonics with −14.8 dB of conversion gain (CG) from P_in = +13 dBm of the balanced input, while the 260 GHz quadrupler utilizes quadruple-push pairs which achieves CG = −16 dB from two +13 dBm of the balanced I/Q driving signals in a 65 nm digital CMOS process.