United States Patent 9512863-Silicon alignment pins: an easy way to realize a wafer-to-wafer alignment

United States Patent 9512863
Inventors:
Jung-kubiak, Cecile (Pasadena, CA, US) 
Reck, Theodore (Pasadena, CA, US) 
Thomas, Bertrand (Bonn, DE) 
Lin, Robert H. (Chino, CA, US) 
Peralta, Alejandro (Huntington Beach, CA, US) 
Gill, John J. (La Crescenta, CA, US) 
Lee, Choonsup (La Palma, CA, US) 
Siles, Jose V. (Pasadena, CA, US) 
Toda, Risaku (Glendale, CA, US) 
Chattopadhyay, Goutam (Pasadena, CA, US) 
Cooper, Ken B. (Glendale, CA, US) 
Mehdi, Imran (South Pasadena, CA, US)

http://www.freepatentsonline.com/9512863.html 

A silicon alignment pin is used to align successive layers of components made in semiconductor chips and/or metallic components to make easier the assembly of devices having a layered structure. The pin is made as a compressible structure which can be squeezed to reduce its outer diameter, have one end fit into a corresponding alignment pocket or cavity defined in a layer of material to be assembled into a layered structure, and then allowed to expand to produce an interference fit with the cavity. The other end can then be inserted into a corresponding cavity defined in a surface of a second layer of material that mates with the first layer. The two layers are in registry when the pin is mated to both. Multiple layers can be assembled to create a multilayer structure. Examples of such devices are presented.