Dissertation Talk: Mm-wave/Terahertz Circuits and Systems for Wireless Communication

Dissertation Talk: Mm-wave/Terahertz Circuits and Systems for Wireless Communication

Presentation: Departmental | May 2 | 3-4 p.m. | 2108 Allston Way (Berkeley Wireless Research Center), BWRC Classroom

http://events.berkeley.edu/index.php/calendar/sn/eecs.html?event_ID=77970

Sponsor: Electrical Engineering and Computer Sciences (EECS)

The mm-wave/sub-terahertz band offers several GHz of spectrum for high data rate communication applications. One could envisage such links for short-range wireless chip-to-chip communication in form factor constrained devices (wireless in a box) and also for long-range high-speed communication (using phased arrays or lenses). CMOS technology offers a potential solution to these applications due to its low cost and high level of integration. The short free-space wavelength (typically in the mm range) at these frequencies allows the antennas to be integrated on the silicon die thereby obviating the need for expensive packaging. This also allows the antenna design to be co-optimized with the rest of the circuitry thereby achieving a more efficient solution. However, the design at these frequencies is especially challenging due to the high free-space path loss and lossy passives and low cut-off frequency of CMOS technology.

This study explores the design of mm-wave/terahertz transceivers in 65nm bulk CMOS technology. This talk will discuss the design of the first generation mm-wave/terahertz prototype and several keys blocks such as switching power amplifiers and wide-band 60 GHz low noise amplifiers used in this design. Measurements results from the PA and the system will be discussed. The latter portion of the talk focuses on the design of a fully integrated 240 GHz sub-terahertz transceiver in 65 nm bulk CMOS technology. In particular, the transmitter involves two on-chip slotted loop antennas to achieve beam forming. Due to the low cut-off frequency of CMOS technology, harmonic generation techniques are employed to generate the sub-terahertz carrier. A simplified receiver architecture is employed to improve the overall noise figure and reduce the power consumption. Using a QPSK modulation scheme, the sub-terahertz wireless link achieves a maximum data rate of 16 Gbps with an energy efficiency of 30 pJ/bit, demonstrating the best know efficiency and a first fully operational link at these frequencies in CMOS technology.