Interconnects in CMOS technology can suffer from high resistivity as they become thinner and smaller. At millimeter-wave and terahertz frequencies, this problem is even more severe. As a result, intra-/inter-chip wireline communications can limit overall system performance. Chip-to-chip wireless communication using on-chip antennas can potentially overcome the limitations of broadband wireline signal transmission. As the terahertz band generates increased interest, nanoscale CMOS technology has demonstrated the potential to be used at these frequencies. Recently, a fully integrated 210-GHz transceiver based on 40-nm CMOS technology was developed by researchers from San Jose State University. This transceiver, which employs on-off-keying (OOK) modulation, utilizes wireless chip-to-chip communication.
The transceiver’s receiver (Rx) contains a modified on-die dipole antenna. A similar on-chip antenna is also used in the transmitter (Tx) path. The Rx consists of an eight-stage low-noise amplifier (LNA), while the power amplifier (PA) that was incorporated into the Tx was designed with a four-stage differential topology. A triple-push, circular-geometry, voltage-controlled oscillator (VCO) was employed in the phase-locked loop (PLL). The transceiver achieved equivalent isotropically radiated power (EIRP) of +6.8 dBm. It also attained a data rate of 10.7 Gb/s over a 1-cm distance between the Rx and Tx. See “A 210 GHz Fully-Integrated OOK Transceiver for Short-Range Wireless Chip-to-Chip Communication in 40 nm CMOS Technology,” IEEE Transactions on Terahertz Science and Technology, Sept. 2015, p. 737.