DOTFIVE is a three-year IP proposal for a very ambitious project focused on advanced RTD activities necessary to move the Silicon/germanium heterojunction bipolar transistor (HBT) into the operating frequency range of 0.5 terahertz (THz) (500 gigahertz GHz) enabling the future development of communication, imaging or radar Integrated Circuits (IC) working at frequencies up to 160 GHz. For a given lithography node bipolar transistors and more recently HBT have always led the frequency race compared to MOS devices, while offering higher power density and better analogue performances (transconductance, noise, transistor matching).The main objective of this highly qualified consortium is to establish a leadership position for the European semiconductor industry in the area of millimeter wave (mmW) by research and development work on silicon-germanium (SiGe) based transistor devices and circuit design capabilities and know-how. SiGe HBT is a key reliable device for applications requiring power > few mW (future MOS limitation) and enabling high density, low cost integration compared to III-V.DOTFIVE vision can be summarised as follows:The overall grand goal of DOTFIVE is to offer silicon based cost effective technologies for the integration of complete electronic functions in the millimeter wavelength (1mm-10mm) range (or 30GHz-300GHz). To achieve the mid range circuit operating frequency Fc ~150GHz we need at least transistors with Fmax~= 3 Fc ie: ~500GHz or .5THz at RT. In 2007 at time of proposal the world-class SiGe Heterojunction Bipolar Transistor technologies offered were in the ~250 GHz range. To DOUBLE the HBT performance in 3 years (faster than ITRS roadmap) the consortium had to assemble a consortium capable of:
a) Theory, modelization, characterization capability
b) SiGe HBT processing capability
c) mmW circuit design capability With these objectives in mind, the consortium thrived to work somewhat like a VIRTUAL LAB «mmW EUROLAB » for a period of 42 months.Objectives and key results by period:
Year 1 Measurable Objectives year 200820092010 targets fmax / td = 300GHz / 3.5ps
400 GHz model libraryfmax / td = 400GHz / 3 ps
500 GHz model library
fmax / td = 500GHz / 2.5ps
The pressure to define a quantifiable Figure of Merit (FoM) push the consortium to adopt 2 FoM, (Fmax and td).Thus the consotium took the goal to set a common FoM methodology.After year 1 a common set of methodology was accepted across the consortium (test pattern, extraction technique, measurement strategy, models etc…) AND in 2008 all 4 technology providers reached or exceeded Fmax 300GHZ.
Year 2“Measurable Objectives” defined; implementation based on learning cycle from Y1:2009: target fmax / td = 400GHz / 3 ps 500 GHz (td is the CML RingOscillator delay time)
Based on accepted methodology within the consortium (test pattern, extraction technique, measurement strategy, models etc…) in 2009 3 technology providers reached or exceeded Fmax 400GHz with IMEC demonstrating G1G architecture & IHP its 2nd generation HBT At the end of Year 2, review the situation could be summarized on table below:
Then project continued in Year 3 and for the 6 months extension granted by the European Commission.
Year 3 (+ 6 months extension)“Measurable Objectives” defined; implementation based on learning cycle Y2
1 2010: target fmax / td = 500GHz / 2.5ps (td is the CML RingOscillator delay time)During P3 DOTFIVE Consortium delivered OUTSTANDING RESULTS. In WP2 the DPSA-SEG HBT architecture pretty much ran out of steam. The key issue is the extrinsic base resistance. BUT WP3 had 3 novel architectures to propose thanks to continuous effort through the extra semester of 2011. Consortium knew upfront that 500 GHz was a challenging goal. P3 is the time when we saw the benefit of the “split technology approach” where WP2 is concentrated on the evolutionary technology concept and WP3 on the disruptive technology concept. WP3 is showing the direction where the future of SiGe HBTs is
WP2 & 3 provided outstanding opportunity to design activity of WP5 to shine with many world firsts in term of circuit design.In WP1/4: In 2009 consortium evidenced shortcomings to the HiCUM model prompting a quick fix, the so-called “reverse Early effect” was transformed into a physics based model and deployed by CAD vendors worldwide. Low temperature (1.6°K) electrical characterization yielded insights where HBT improvements are required. The Ultimate SiGe HBT limit study (Ft ~1.2 THz) was a impressive collaborative effort.In WP5: Several world firsts in term of performances of circuit blocks. Above-fmax SiGe circuits (multipliers, harmonic mixers) show a viable path for true silicon terahertz applications. 140GHz automotive radar was demonstrated.
Faster circuits still needed to improve sensitivity and output power.
Although global project objectives are REACHED, the projected TIMELINE HAS SLIPPED due essentially to slower technology learning cycle in WP2 but the will to complete the 3 predefined learning cycles prevailed.
WP1 & 4 partners have behaved like a European Advanced TCAD/model infrastructure capable to lead at world level. The P3 main achievements are:
The 4 technology providers (2 industrialists/2 institutes) made OUTSTANDING PROGRESS towards the main objective:From the previous table we obtain the final results summarized in the table below :
With 64 deliverables, 44 milestones and 76 publications in open literature (journals and conferences) DOTFIVE was very productive. 1 patent was awarded and a second one is pending 2 best paper awards were attributed to DOTFIVE publications
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