Abstract-Design of Switching-Mode CMOS Frequency Multipliers in Sub-Terahertz Regime

Jung-Dong Park¹⁾

1) Graduate of School of Engineering, University of California

 [Advance Publication] Released September 03, 2014

https://www.jstage.jst.go.jp/article/elex/advpub/0/advpub_11.20140806/_article

Switching mode CMOS frequency multipliers are studied in sub-Terahertz regime. Analysis on the multiplier architectures and optimal gate bias at CMOS switch are investigated to maximize output power at designated harmonics. Utilizing a differential pair, a 195GHz tripler having a hair-pin filter is designed to maximize 3^rd harmonics with -14.8dB of conversion gain (CG) from P_in=+13dBm of the balanced input, while the 260GHz quadrupler utilizes quadruple-push pairs which achieves CG=-16dB from two +13dBm of the balanced I/Q driving signals in a 65nm digital CMOS process.